Course description

Very Large Scale Integration(VLSI) is a way through which integrated circuit is created by integrating millions of transistors into a single chip. This design has become the most happening field of electronics and is finding its application in diverse range of electrical equipment like computer peripherals, cell phones, satellites, defense aerospace, consumer electronics, set top entertainment boxes and several other devices. All those candidates, who are looking to build a career in VLSI field, Vector Institute offers training program in VLSI technologies, which is designed to meet the contemporary demands of the industry. Our VLSI technologies course trained candidates with various domains of chip design.

Unique Service Point(USP)

VLSI Design Course imparts ASIC, FPGA design flows, and trains engineers extensively on the VLSI design methodologies, CMOS, VHDL, Verilog and System Verilog. An unprecedented demand for the expert professionals of VLSI Design is encouraging us to offer course that geared towards meeting the increasing demand of the electronic industry.

What is a VLSI?

Very-large-Scale Integration is the process of creating an integrated circuit by combining hundreds of thousands of transistors or devices into a single chip.

What is the course duration?

Course Duration is 3 months/12 months.

What are the career options in this course?

Pivate firms offer plenty of job opportunities for candidates who have completed post graduation in VLSI than that in government sector firms. Aspirants can start their career as Application Consultants, Field Application Engineer and Design Engineer in various firms.

Who is eligible for this course?

B.E or Bachelor of Technology in Electronics, Telecommunications or Computer Science.


  • MOS Fundamentals and Characterization
  • NMOS/PMOS/CMOS Technologies
  • Fabrication Principles
  • Different Styles of Fabrication for      NMOS/PMOS/CMOS
  • Design with CMOS Gates
  • Characterization of CMOS Circuits
  • Scaling Effects
  • Sub-Micron Designs
  • Parasitic Extraction and Calculations
  • Subsystem Design
  • Layout Representation for CMOS Circuits
  • Design Exercise using CMOS
  • Introduction of IC Design
  • Different Methodologies for IC Design
  • Fabrication Flows and Fundamentals

  • 2.Networking and TCP/IP Applications

  • Network Structure
  • Classifications and Topologies
  • Switching and Routing
  • Gateway, Repeater, Hub,Bridge
  • OSI & TCP/IP Protocol
  • Layers
  • Physical & Logical
  • Addresses
  • ARP & RARP

  • 3.VHDL

  • VHDL Overview and Concepts
  • Levels of Abstraction
  • Entity, Architecture
  • Data Types and declaration
  • Enumerated Data Types
  • Relational, Logical, Arithmetic Operators
  • Signal and Variables, Constants
  • Process Statement
  • Concurrent Statements
  • When-else, With-select
  • Sequential Statement
  • 4.ASIC Flow

  • EDA Tools / CAD Flow for IC Design
  • Simulation/Synthesis using ASIC libraries
  • Clock Tree Synthesis
  • False paths / Multi cycle paths / Critical      paths
  • Design for Testability (DFT)
  • Scan Insertion / Types of Scan
  • Fault Models
  • Logic BIST, Memory BIST, ATGP,      Boundary Scan
  • Pattern Compression
  • Scan Diagnostics
  • Layout Design
  • Placing and Routing

  • 5.System Verilog

  • Core Features
  • Introduction to System Verilog
  • System Verilog Declaration spaces
  • System Verilog Literal Values and Built-in      Data Types
  • System Verilog User-Defined and      Enumerated Types
  • System Verilog Arrays, Structures and      Unions
  • System Verilog Procedural Blocks, Tasks      and Function
  • System Verilog Procedural Statements
  • Modelling Finite State Machines with      System Verilog


  • ASIC / FPGA Design Fundamentals
  • Advanced Digital Design